Circuits and Techniques for 5G Mobile Communications and Beyond
Professors Peter Asbeck, Drew Hall, Ian Galton, Patrick Mercier, and Gabriel Rebeiz
University of California, San Diego
The research consists of five projects. The projects are separate but are related in that they will develop critical circuits for 5G and future-generation wireless applications. The projects are out-lined briefly in Sections II through VI below.
High Efficiency Power Amplifiers and Transmitters for 5G and 6G Applications
Project Leader: P. Asbeck
This project investigates novel architectures and circuits for sub-6GHz 5G, mm-wave 5G, and introductory 6G power amplifiers (PAs).
Research for sub-6GHz 5G systems will focus on basestation GaN-based PAs that have improved efficiency by tailoring the power supply voltage for the power level to be delivered. This strategy is known to be effective for envelope tracking (for low signal bandwidths) and average power tracking (for slow variations in power required). In this work, we will tailor the dynamic power supply response time to the symbol rate, which will allow optimization of both the power supply and the RF amplifier. With participation of Prof. Hanh-Phuc Le, a GaN-based rapid switching dc-dc converter will be developed for the high efficiency supply.
For 5G mm-wave applications, we will focus on refinement of the adaptively biased asymmetric Doherty amplifiers currently being developed in our laboratory, and investigate digitally-assisted analog predistortion techniques to maintain linearity and improve tolerance to VSWR.
For initial explorations of higher frequency bands for 6G, we will implement high efficiency CMOS amplifiers at 70-75GHz, which can be used near term in backhaul and in E band point-to-point applications. We will investigate PAs for significantly higher power (>1W) by researching the use of CMOS ICs closely-coupled to final stage PAs implemented in GaN.
Digital PLLs with Sub-100 fs jitter for Local Oscillator Frequency Synthesis
Project Leader: I. Galton
High-order modulation formats, such as 1024 QAM, enable very high wireless data rates with high spectral efficiency. However, the higher the modulation order, the higher the performance required of the phase-locked loops (PLLs) used for transceiver local oscillator generation. PLLs with sub-100 fs clock jitter are necessary for the high-performance modes of 5G, and it is likely that 6G jitter requirements will be even more aggressive. Digital PLLs are particularly attractive for handset transceivers, but the few that have been published with sub-100 fs jitter have critical design challenges that make them temperamental to implement, and they have yet to be demonstrated in high-volume commercial products.
The research will address this problem by developing a digital PLL architecture capable of robust sub-100 fs jitter performance. The PLL will be a next-generation version of the FDC-PLL that was originally developed by our group and is currently in widespread commercial use. The enabling new feature will be a time amplifier prior to the phase detector that amplifies the time difference between corresponding reference and divider edges. Unlike prior time amplifiers used in PLLs to reduce jitter, the new time amplifier has a wide useable input range and high linearity. The linearity will be further enhanced via a digital calibration algorithm that measures error from time amplifier nonlinearity in real time (not as an autocalibration technique) and applies a correction signal to compensate for the error. A demonstration IC will be developed in 22 nm CMOS technology with a 76.8 MHz reference and an output fre- quency that spans 7-8 GHz, that targets an absolute jitter of less than 90 fs, in-band fractional spurious tones less than −65 dBc, and state-of-the-art power consumption from a 0.8 V supply.
Powering and Communicating with the Internet-of-(Medical)-Things (IoMT)
Project Leader: D. Hall
Wearable devices have the potential to disrupt healthcare by enabling a remote interface between doctor and patient. However, most wearable sensors today, including smartphones and fitness trackers, are limited to motion sensing. They sense few, if any, medically relevant physiological parameters. We re- cently developed an implantable biomedical device for continuous in vivo biomarker measurements that could transform healthcare and enable precision medicine – the concept of accurately tailoring pharmaco- logical treatment to the individual. These “BioMote” sensors are the size of a single grain of rice (< 1 mm3) and injected through a 16-gauge needle into interstitial fluid (ISF) – the quasi-stationary extracellu- lar fluid surrounding cells. To reduce the size and potential toxicity, the BioMote is powered wirelessly. Wireless power transmission and backscatter communication (via load shift keying) is widely used today to read RFID tags and is a promising approach to enable ultra-low-power implantable mm3-scale implantable medical devices. However, there are significant challenges translating such an approach to biomedical ap- plications that have significant path loss due to tissue absorption (~80 dB) and transmitter leakage, which acts as a blocker (>70 dB) at the carrier frequency for the receiver.
In this effort, we will design a low-power wearable “relay” device that can wirelessly power and communicate with body-worn and implanted IoMT devices. The relay will then send the data to an aggre- gator for further processing using an ultra-low power transmitter in the Medical Implant Communication System (MICS)-band. To address the transmitter leakage, we propose a feedforward transceiver cancella- tion scheme that will not desensitize the receiver and enable recovery of the backscattered signal. The MICS transmitter will consist of a new technique for process, voltage, and temperature (PVT)-robust, cal- ibration- and regulation-free synthesis of the RF carrier based on generating poly-phasors at 50 MHz and combining them with an 8× edge combiner to generate the 400 MHz carrier without a PLL. An inverse class-E power amplifier will be implemented for high efficiency at low output power (-17.5 dBm). Open- loop operation will allow aggressive duty-cycling (< 40 ns start-up time). If fully funded, we expect to achieve state-of-the-art performance from the relay device and the MICS transmitter.
Low-Power mm-wave Circuits for Efficient Mobile Systems Beyond 5G
Project Leader: P. Mercier
Emerging applications in mobile devices such as augmented/virtual reality (AR/VR), battery- powered wireless high-definition video systems, and lightweight drones all require increasingly high throughput communications. For this reason, mm-wave communication systems are an attractive option. However, such applications also require lightweight, low-power designs in order to maximize battery life. Unfortunately, most mm-wave transceivers designed for mobile 5G applications do not place power con- sumption at the top of the list in terms of optimization priority. Placing power consumption at the top of the list, with performance a close second, presents an opportunity to research and develop new radio ar- chitectures and circuit techniques to enable new classes of wireless applications beyond current 5G speci- fications.
In this work, we specifically aim to design mm-wave communication systems that improve energy efficiency and reduce power consumption over conventional approaches by at least an order of magni- tude, all towards enabling next-generation applications beyond the capabilities of 5G systems envisioned in the immediate future. We aim to achieve this by exploiting the main resource offered at mm-wave fre- quencies: bandwidth. Rather than building complex OFDM waveforms with x-QAM symbols that require extremely linear front-ends, precision frequency references, and sophisticated basebands, it makes sense for these types of battery-powered applications to exploit lower-index modulation schemes that enable lower-complexity and therefore lower power implementations as a trade-off with spectral efficiency. Since bandwidth can be wide, energy efficiency can be obtained along with low-power operation by in- creasing modulation frequencies without a commensurate increase in linearity or phase noise require- ments. Further exploiting bandwidth towards extremely SNR-friendly schemes such as 16-FSK can help to improve link budgets while still supporting extremely high throughput. We plan to design radio front- ends along these lines, while also exploring several circuit-level innovations, including low-power inte- ger-N frequency synthesis based on temperature-compensated FBAR resonators, and low-noise high-gain front-end structures based on regenerative amplifier concepts./
Directional Antennas using Phased-Arrays for 6G
Project Leader: G. Rebeiz
6G with 100+ Gbps communication links and operating in the frequency range of 60-200 GHz will require directional antennas for improved SNR due to the high space-loss factor at these frequencies. This can be done using lens based-systems such as dielectric lenses directly on the RFIC, or using phased-arrays with 16 to 64-elements. The lens-based systems employ a single amplifier per beam are useful for very short distances such as 10-30 cm. Phased-arrays, in contrast, enable 16 to 64-amplifiers to add coherently in a single beam, thus greatly improving the SNR, but are hard to build at 100 GHz and above. Also, they require phase-shifters at 60-200 GHz, which can be done either in the RF, LO or IF do- mains, each having its own drawbacks (loss for the RF domain, mixers on each element for the LO and IF domains). Finally, at 100-200 GHz and above, there is simply little available space per element, as the antennas are placed on a grid of < 0.75-1.5mm.
This work researches different solutions for millimeter-wave 6G phased-arrays, from a topology, architecture and energy perspective, and how each of these will influence the design of the RFIC. Also, different high-efficiency antennas will be considered such as dielectric resonator antennas on top of the RFIC to laminate-type microstrip antennas in the package. Also, 1-D and 2-D scanning designs will be considered as each will result in completely different antennas and phased-array design. The goal is to build a high-efficiency phased-array operating in the 100-200 GHz range and capable of sustaining a very wideband modulation scheme for 100+ Gbps links.